A year ago, NXP coverage reached the i.MX RT1062 and LPC55S69, with about 40% of each family's peripherals producing full HAL output. That coverage has changed substantially. Here is the current position for each vendor family, beyond a single headline percentage.
What Support Includes
Embedd produces drivers at two levels. Register map generation creates a C header containing the full register struct, bitfield masks and shifts, reset values, and access annotations. Full HAL generation also supplies configuration APIs, initialization routines, read/write helpers, interrupt wiring, and unit test stubs. Since not every peripheral reaches both levels, the distinction is important when evaluating a particular chip.
A chip marked "supported" in our library produces at least its register map. That alone can remove much bring-up work by avoiding offset, bitfield alignment, and reset value errors, even when you implement the HAL yourself. Teams seeking full HAL output can use docs/supported-chips.html to see which peripheral families reach each level.
NXP Coverage
The i.MX RT line has our broadest NXP coverage. RT1062 and RT1064 produce full HAL output for UART (LPUART), SPI (LPSPI), I2C (LPI2C), FlexPWM, and basic GPIO. DMA and FlexRAM initialization remain at register-map tier because their multi-register interaction requires ordering choices that the datasheet alone cannot determine.
For the Kinetis K22, K64, and K66, most peripherals are at register-map tier, while UART and SPI have full HAL support. The LPC55S69 provides full HAL for FLEXCOMM UART, SPI, and I2C. Handling its software-selected UART or SPI overlays required a parsing extension for the mode-dependent registers.
The i.MX 8 family remains unsupported. Its security monitor, DDR controller, and boot ROM interactions exceed what datasheet-based generation can reliably cover.
TI Coverage
TI uses the most varied datasheet format among the four vendors here. A single family may have a 4,000-page technical reference manual, with register tables separated across sections and repeated headers formatted inconsistently. Common TI tables parse reliably, but older Tiva-C and MSP432 TRMs use fallback modes that can sometimes omit fields.
The CC2652 and CC1352 SimpleLink wireless families produce full HAL for UART, SPI, I2C, ADC, and GPIO. RF core and BLE stack registers appear in the register map, but have no HAL because TI's proprietary RF driver stack owns those interfaces and direct access is not appropriate.
MSP432E4 provides full HAL for UART, SSI (SPI), I2C, and basic timers. MSP430 is currently register-map only. Its 16-bit SFR access model, covered in our MMIO patterns post, needs different generator output from the 32-bit path, with work underway for Q3 2026.
ST Coverage
STM32 is our most mature family, supported by well-structured datasheets, strong SVD coverage for most devices, and extensive pilot-program test feedback.
STM32F4 (Cortex-M4, 168 MHz range) has full HAL for USART, SPI, I2C, TIM (basic and advanced), ADC, DMA, and GPIO. STM32L4 adds LPUART, RTC, and LPTIM to that set. STM32H7 (Cortex-M7, 480 MHz) supports USART, LPUART, SPI, QSPI, I2C, TIM, ADC, and DMA. H7 memory protection unit setup remains at register-map tier.
STM32G0 and STM32G4 entered the full HAL tier in March 2026. STM32WB provides full HAL for application-core peripherals, while its M0+ radio co-processor registers appear in the register map without a HAL layer.
Nordic Coverage
Nordic nRF52 devices provide full HAL for commonly used peripherals including UARTE, SPIM, SPIS, TWIM, TWIS, SAADC, TIMER, RTC, GPIOTE, and PPI. The nRF52840 USBD controller remains register-map only because Nordic SoftDevice and Zephyr USB both require direct USBD access that does not fit a standard HAL model.
The nRF9160 LTE-M/NB-IoT SiP provides full HAL for non-modem peripherals: UARTE, SPI, I2C, TIMER, and ADC. Modem registers are excluded because Nordic's proprietary modem firmware owns them and application code should not access them, as with radio registers on TI and Nordic wireless devices.
nRF54H20 and nRF54L15 joined the chip library in April 2026 at register-map tier. Their multi-core design and new peripheral names required parser changes. Full HAL generation for nRF54 is the main Nordic roadmap item for Q3 2026.
Known Parsing Limits
Two parsing issue categories affect coverage quality across all four vendors.
The first concerns tables split across PDF pages. Our parser handles identical headers and contiguous rows, but some datasheets vary column widths or header formatting between pages, producing duplicate or missing rows. The affected register map receives a detection comment, and that register group is limited to register-map tier.
The second involves ambiguous bitfield descriptions. When multi-bit enumerations appear in prose, we extract values only when the wording follows a recognizable pattern. Narrative-only descriptions still produce masks and shifts, while the header comment carries the enumeration details instead of typed enum constants. This is a generator quality gap, not a coverage gap, since the register remains correctly mapped.
Both issues are recorded in the tracker with chip-specific notes. To flag an affected chip, peripheral, and datasheet version, use the request form at docs/supported-chips.html.
